<!doctype html><html lang=en><head><meta charset=utf-8><meta name=viewport content="width=device-width,initial-scale=1,viewport-fit=cover"><base href=https://www.lowrisc.org><link rel=icon type=image/png sizes=32x32 href=/favicon.png><title>Soc structure updates &middot; lowRISC: Collaborative open silicon engineering</title><link href=/main.21c9d.css rel=stylesheet><script type=application/javascript>var doNotTrack=false;if(!doNotTrack){(function(i,s,o,g,r,a,m){i['GoogleAnalyticsObject']=r;i[r]=i[r]||function(){(i[r].q=i[r].q||[]).push(arguments)},i[r].l=1*new Date();a=s.createElement(o),m=s.getElementsByTagName(o)[0];a.async=1;a.src=g;m.parentNode.insertBefore(a,m)})(window,document,'script','https://www.google-analytics.com/analytics.js','ga');ga('create','UA-53520714-1','auto');ga('send','pageview');}</script></head><body><header><nav class="navbar navbar-expand-md navbar-light"><div class=container><a class=navbar-brand href=#><img src=/img/logo/logo-dualcolor.svg alt=lowRISC></a>
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<span class=navbar-toggler-icon></span></button><div class="collapse navbar-collapse" id=navbarCollapse><ul class="navbar-nav ml-auto"><li class=nav-item><a href=/our-work class=nav-link>Our work</a></li><li class=nav-item><a href=/open-silicon class=nav-link>Open Silicon</a></li><li class=nav-item><a href=/community class=nav-link>Community</a></li><li class=nav-item><a href=/blog class=nav-link>Blog</a></li><li class=nav-item><a href=/jobs class=nav-link>Jobs</a></li><li class=nav-item><a href=/about class=nav-link>About us</a></li><li class=nav-item><a class="btn lr-navbar-btn-gh" href=https://github.com/lowrisc>GitHub</a></li></ul></div></div></nav></header><main role=main><div class=container><h1>Soc structure updates</h1><p>Thanks to the continuous development from the RISC-V group at UC Berkeley,
there are a lot of structure changes and extra features incorporated in this
release.</p><p><a name=figure-overview></a><img src=../figures/lowRISC_soc.png alt=Drawing style="width:500px;padding:20px 0"></p><ul><li><p><strong>Shared TileLink MEM network for both cached (memory) accesses and uncached (IO) accesses.</strong><br>In the previous untethered release, cached memory accesses and uncached IO
accesses are separated early in the L1 D$, which has the benefit of small
on-chip interconnects and less interference to the memory interconnect from IO
transactions. However, this leads to troubles when a peripheral, such as a
DMA, needs to access the memory (L2 cache). This release follows the choice
from the upstream Rocket design that separates uncached IO transactions from
cached memory accesses at the coherent TileLink MEM network. As a result, the
debug MAM module can access memory as well as all IO space by a single access
point to the MEM network.</p></li><li><p><strong>A global memory space regulator: address map</strong><br>A static data structure is added into the Rocket-chip to regulate the size
and the R/W/X permission of all memory sections. It uses a hierarchical map to
store all memory sections. For the standalone FPGA demo, the map should look
like:<br><br>&nbsp;&nbsp;<code>&lt;&quot;io&quot;, 0x00000000-0x7fffffff&gt;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>&lt;&quot;int&quot;, 0x00000000-0x3fffffff&gt;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>&lt;&quot;bootrom&quot;, 0x00000000-0x00001fff, RX&gt;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>&lt;&quot;rtc&quot;, 0x00002000-0x00002fff, RW&gt;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>&lt;&quot;prci0&quot;, 0x00003000-0x00003fff, RW&gt;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>&lt;&quot;ext&quot;, 0x40000000-0x7fffffff&gt;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>&lt;&quot;bram&quot;, 0x40000000-0x4000ffff, RWX&gt;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>&lt;&quot;flash&quot;, 0x41000000-0x40ffffff, RX&gt;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>&lt;&quot;uart&quot;, 0x42000000-0x42001fff, RW&gt;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>&lt;&quot;spi&quot;, 0x42002000-0x42003fff, RW&gt;</code><br>&nbsp;&nbsp;<code>&lt;&quot;mem&quot;, 0x80000000-0xffffffff, RWX&gt;</code><br><br>Note that the base address of each memory section is calculated automatically during the Chisel compilation. For a detail look of the address map, please read the related part in <code>$TOP/src/main/scala/Configs.scala</code> (initialization of the address map) and <code>$TOP/junctions/src/main/scala/addrmap.scala</code> (implementation of the address map).</p></li><li><p><strong>Boot ROM</strong><br>A boot ROM is added into the SoC, which should always located at the reset address (0x00000000 by default). The current boot ROM has two parts: The first several instructions redirect PC to the on-chip BRAM if it is enabled or to the DDR RAM. The rest of the ROM has a configuration string, which stores a simplified device tree. This configuration string identifies the number and types of processors on chip along with the address map. For the standalone FPGA demo, the configuration string should read as:<br><br>&nbsp;&nbsp;<code>platform {</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>vendor lowRISC;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>arch rocket;</code><br>&nbsp;&nbsp;<code>};</code><br>&nbsp;&nbsp;<code>rtc {</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>addr 0x2000;</code><br>&nbsp;&nbsp;<code>};</code><br>&nbsp;&nbsp;<code>ram {</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>0 {</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>addr 0x80000000;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>size 0x8000000;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>};</code><br>&nbsp;&nbsp;<code>};</code><br>&nbsp;&nbsp;<code>core {</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>0 {</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>0 {</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>isa rv64imafd;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>timecmp 0x2008;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>ipi 0x3000;</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>};</code><br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<code>};</code><br>&nbsp;&nbsp;<code>};</code><br><br>This configuration string is automatically generated by <code>makeBootROM()</code> in <code>$TOP/src/main/scala/LowRISCChip.scala</code> Note that not all sections in address map is recorded in the configuration string. We will rectify this soon. With this configuration string in the boot ROM, bootloaders and the Linux kernel are able to probe the SoC structure without external device tree files.</p></li></ul></div></main><footer class=lr-footer><div class=container><div class=row><div class="col-lg-2 d-none d-lg-block"><img src=/img/logo/logo-dualcolor.svg width=150px></div><div class=col><p>The text content on this website is licensed under a <a href=https://creativecommons.org/licenses/by/4.0/>Creative Commons Attribution 4.0 International License</a>, except where otherwise noted. No license is granted for logos or other trademarks. Other content &copy; lowRISC Contributors.</p><a href=/privacy-policy>Privacy and cookies policy</a>
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